(1) Field of the Invention
The present invention relates to a semiconductor device comprising a hermetically sealed package and an integrated-circuit chip packed therein and more particularly to an improvement in the electrical connection between the lower surface of the chip and one of the leads of the package.
(2) Description of the Prior Art
In the process of producing a semiconductor device, a packaging step must be carried out. There are various kinds of well-known integrated-circuit packages in the art. For example, in the case of a dual in-line package (DIP), such as a so-called Cerdip, illustrated in FIGS. 1 and 2, a package substrate 1 of ceramic has a cavity in the center portion. A gold paste is applied on the bottom surface of the cavity and is heated at a temperature from 800.degree. C. to 950.degree. C. to form a gold layer 2. Then a glass paste having a low melting point is applied on the surface of the ceramic substrate 1, except for the cavity, and is pre-baked at a temperature of about 400.degree. C. to form a glass layer 3. A lead frame which comprises leads 4 and is made of an Fe-Ni-Co alloy (e.g., Kovar) or an Fe-Ni-alloy (e.g., 42 Alloy) is set on the glass layer 3, and the ceramic substrate 1 is heated at a temperature of about 450.degree. C. to melt the glass layer 3 so that the leads 4 stick to the glass layer 3. In order to attach an integrated-circuit chip 5 to the package substrate 1 while the substrate 1 is being heated at a temperature of from 400.degree. C. to 450.degree. C., the chip 5 is placed on the gold layer 2 in such a manner that the gold layer 2 is scrubbed with the chip 5. As a result, the silicon of the integrated-circuit chip 5 is alloyed with the gold of the gold layer 2 to form a eutectic brazing alloy having a low melting point. Therefore, by forming a brazing alloy, the chip can be attached to the package substrate 1.
In order to ground the integrated-circuit chip 5 at the lower surface thereof, generally, a terminal metal chip 6 is attached to the gold layer 2, prior to IC chip attaching step or a wire bonding step, to create predetermined electrical connections between the integrated-circuit chip 5 and the leads 4. If the terminal metal chip 6 is not provided, when an aluminum micro-wire (i.e., a bonding wire) is used to connect the gold layer 2 to a lead of the frame to be grounded, the aluminum and gold commonly form an intermetallic compound of purple or white plague during a sealing step carried out at a temperature from 400.degree. C. to 500.degree. C. The compound weakens the bond strength and decreases the electric conductivity, with the result that bond failure may occur. The terminal metal chip 6 comprises, e.g., a metal base 7 being e.g., of an Fe-Ni-Co alloy or an Fe-Ni alloy, an aluminum-silicon (AlSi) alloy or aluminum (Al) thin layer 8 formed on the upper surface of the base 7, and a gold-germanium (AuGe) alloy thin layer 9 formed on the lower surface of the base 7, as is illustrated in FIG. 3. Such a terminal metal chip is disclosed in Japanese Unexamined Patent Publication No. 55-27615. The terminal metal chip 6 can be produced by putting an Al or AlSi film and a AuGe film on the upper surface and the lower surface of a metal plate, respectively, rolling the films with pressure rollers to form a laminated plate, and punching the plate. The obtained metal chip has a predetermined shape, e.g., a circular shape, a rectangular shape, etc. In order to attach the terminal metal chip 6 to the package substrate 1 while the substrate 1 is being heated at a temperature from 400.degree. C. to 450.degree. C., the chip 6 is put on the gold layer 2 so as to bring the AuGe layer 9 in contact with the gold layer 2. Then the gold layer 2 is scrubbed with the chip 6. As a result, the AuGe layer 9 and the gold layer 2 are melted and alloyed. After cooling, the chip 6 sticks to the gold layer 2, i.e., the substrate 1. Then aluminum wires 10 are attached between bonding pads (i.e., contact areas) 11 of the integrated-circuit chip 5 and the terminal areas of the leads 4 by using an ultrasonic bonding technique, as is illustrated in FIGS. 1 and 2. During the wire bonding step, an aluminum wire 12 is also attached between the Al or AlSi layer 8 of the terminal metal chip 6 and a predetermined lead 4A. Therefore, the integrated-circuit chip 5 can be grounded via the terminal metal chip 6.
Finally, a ceramic cap 13 (FIG. 1) with a pre-baked glass layer 14 having a low melting point is put on the glass layer 3 and the lead 4, and the substrate 1 and the cap 13 are heated at a temperature from 400.degree. C. to 500.degree. C. in a furnace. Since the glass layer 14 has a low melting point similar to that of the glass layer 3 the layer 4 is made of the same material as is the layer 3, the glass layers 14 and 3 melted and are combined into a sealing glass layer. After cooling, a hermetically sealed package is produced.
However, the present inventors found that when the terminal metal chip 6 was bonded to the package substrate 1 the bond strength was remarkably reduced because the AuGe alloy layer between the terminal metal chip 6 and the gold layer 2 alloyed with silicon, which diffused from the integrated-circuit chip 5 through the gold layer 2 during the heat treatment for sealing to form a gold-germanium-silicon (AuGeSi) alloy. A reduction in the bond strength may result in bond failure and thus decrease the reliability of the semiconductor device.